Asymmetrical 17-Level Inverter Topology with Reduced Total Standing Voltage and Device Count

M. Saad Bin Arif, Uvais Mustafa, Shahrin Bin Md Ayob, Jose Rodriguez, Abdul Nadeem, Mohamed Abdelrahem

Resultado de la investigación: Contribución a una revistaArtículorevisión exhaustiva

18 Citas (Scopus)


Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.

Idioma originalInglés
Número de artículo9424556
Páginas (desde-hasta)69710-69723
Número de páginas14
PublicaciónIEEE Access
EstadoPublicada - 2021

Áreas temáticas de ASJC Scopus

  • Informática (todo)
  • Ciencia de los materiales (todo)
  • Ingeniería (todo)


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