TY - GEN
T1 - Novel Three-Phase Multi-Level Inverter with Reduced Components
AU - Salem, Ahmed
AU - Van Khang, Huynh
AU - Robbersmyr, Kjell G.
AU - Norambuena, Margarita
AU - Rodriguez, Jose
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - A new multilevel converter topology is proposed in this paper. Low component count and compact design are the main features of the proposed topology. Furthermore, the proposed converter is a capacitor-, inductor-, and diode-free configuration, allowing reducing the converter footprint, increasing the lifetime and simplifying the control strategy. Further, a comparative study is carried out to highlight the merits of the proposed circuit as compared to existing multilevel topologies. Finally, simulation results for the three-level version using different modulation strategies are presented.
AB - A new multilevel converter topology is proposed in this paper. Low component count and compact design are the main features of the proposed topology. Furthermore, the proposed converter is a capacitor-, inductor-, and diode-free configuration, allowing reducing the converter footprint, increasing the lifetime and simplifying the control strategy. Further, a comparative study is carried out to highlight the merits of the proposed circuit as compared to existing multilevel topologies. Finally, simulation results for the three-level version using different modulation strategies are presented.
KW - fundamental frequency modulation
KW - multilevel inverters
KW - pulse width modulation
UR - http://www.scopus.com/inward/record.url?scp=85084133648&partnerID=8YFLogxK
U2 - 10.1109/IECON.2019.8927732
DO - 10.1109/IECON.2019.8927732
M3 - Conference contribution
AN - SCOPUS:85084133648
T3 - IECON Proceedings (Industrial Electronics Conference)
SP - 6501
EP - 6506
BT - Proceedings
PB - IEEE Computer Society
T2 - 45th Annual Conference of the IEEE Industrial Electronics Society, IECON 2019
Y2 - 14 October 2019 through 17 October 2019
ER -